The present invention relates generally to a silicon-on-insulator (SOI) device and a method for manufacturing the same, and more particularly, to an SOI device which improves both the sensing margin of the floating body cell formed in an SOI substrate and the operational characteristics thereof and a method for manufacturing the same.
Semiconductor devices are constantly proceeding towards higher integration, higher operation speed, and lower power consumption. With this in mind, semiconductor devices that use an SOI substrate in place of the silicon substrate formed of bulk silicon, (that is, an SOI device) are gaining popularity. This is because the semiconductor device formed using the SOI substrate confers advantages that do not exist in the silicon substrate. Examples of these advantages include high speed operation due to a reduced junction capacity, a lower voltage requirement due to a reduced threshold voltage, and prevention of a latch-up phenomenon due to the complete isolation obtainable with the SOI substrate.
Hereinbelow, a conventional SOI device is schematically described.
An SOI substrate includes an SOI substrate composed of a stack structure of a silicon substrate, a buried oxide layer, and a silicon layer. The silicon substrate functions to support the entire SOI device, and the silicon layer serves as a layer on which the SOI device is actually formed. Gates are formed on the silicon layer of the SOI substrate, and junction areas are formed in the silicon layer on both sides of the gates. The junction areas are formed such that the lower ends thereof come into contact with the buried oxide layer. Accordingly, the portions of the silicon layer under the gates (that is, the bodies of transistors) are isolated by the junction areas and the buried oxide layer and are thereby floated.
Therefore, the SOI device has a floating body cell (FBC) in which the bodies of the transistors isolated by the junction areas and the buried oxide layer are floated. Because charges can be stored in the floated bodies, it is not necessary to form capacitors, and accordingly, it is possible to decrease the size of a cell.
However, in the conventional SOI device, when cell size is decreased in order to accommodate the trend toward high integration of a semiconductor device, the volume of the transistor body is reduced, and consequently the charge storage capacity of the body decreases. As a consequence, in the conventional SOI device, it is difficult to adjust the threshold voltage, and therefore the sensing margin of the device deteriorates.
Further, in the conventional SOI device, a punch-through phenomenon occurs between the junction areas formed on both sides of the gates, leading to deterioration in the operational characteristics of the cell transistors.